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Annealing processors are designed to solve combinatorial optimization problems, where the task is to find the best solution from a limited set of possibilities. This has important implications for practical applications in logistics, resource allocation, and drug and materials discovery. In the context of CMOS, a semiconductor technology, the components of the annealing processor must be fully “coupled”. However, the complexity of this coupling directly affects the scalability of the processor.
in a new IEEE access Research led by Prof. Published on January 30, 2024 Researchers led by Dr. Takayuki Kawahara of Tokyo University of Science developed and successfully tested a scalable processor that divides computation among multiple LSI wafers.This innovation was also presented at IEEE 22ND The World Symposium on Applied Machine Intelligence and Informatics (SAMI 2024) will be held on January 25, 2024.
According to Professor Kawahara, We hope to implement high-level information processing directly at the edge, rather than in the cloud or preprocessing for the cloud at the edge. Utilizing the unique processing architecture announced by Tokyo University of Science in 2020, we implemented fully coupled LSI (large-scale integration) on one wafer using 28nm CMOS technology.Furthermore, we design a scalable approach with parallel operating wafers and demonstrate its feasibility using FPGAs (Field Programmable Gate Array) will be launched in 2022.
The team created a scalable annealing processor in this research, which was partially supported by JSPS KAKENHI Grant No. 22H01559, Tokyo University of Science Entrepreneurship Grant (PoC Support Grant), and the Tokyo Metropolitan Government. It uses 36 22nm CMOS computing LSI (large-scale integration) chips and 1 control FPGA. This technology enables the construction of large-scale fully coupled semiconductor systems based on the Ising model (a mathematical model of magnetic systems) with 4096 spins.
The processor uses two different technologies developed by Tokyo University of Science. These include a “spinning thread approach” that enables eight parallel solution searches, as well as technology that reduces wafer requirements by about half compared to conventional methods. Its power consumption requirements are also moderate, with an operating frequency of 10MHz and a power consumption of 2.9W (the core part is 1.3W). This was actually confirmed using a vertex cover problem with 4096 vertices.
In terms of power-to-performance ratio, the performance of this processor is 2,306 times higher than the performance of a fully coupled Ising system simulated on a PC (i7, 3.6GHz) using annealing simulation. In addition, it also surpasses the core CPU and computing chip by 2186 times.
Successful machine validation of this processor shows the possibility of enhanced capacity. Professor Kawahara has a vision for the social implementation of this technology (e.g. entrepreneurship, joint research and technology transfer), “In the future, we will develop this technology and jointly research LSI systems with 2050-level quantum computer computing capabilities. Used to solve combinatorial optimization problems. The goal is to do this using current semiconductor processes, without the need for air conditioning, large equipment or cloud infrastructure. Specifically, we hope to achieve 2M (millions) spins by 2030 and explore leveraging this to create new digital industries. “
In summary, the researchers developed a scalable, fully coupled annealing processor integrating 4096 spins on a single board with 36 CMOS dies. Key innovations, including parallel operations to reduce chipping and simultaneously search for solutions, played a vital role in this development!
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refer to
Author: Taichi Megumi, Endo Akari, Kawahara Takayuki
DOI: https://doi.org/10.1109/ACCESS.2024.3360034
Affiliated institution: Department of Electrical Engineering, Tokyo University of Science
about Tokyo University of Science
Tokyo University of Science (TUS) is a well-known and respected university and the largest private research university in the sciences in Japan, with four campuses in central Tokyo and its suburbs, as well as in Hokkaido. Founded in 1881, the university continues to contribute to Japan’s scientific development by instilling a love of science among researchers, technicians and educators.
With the mission of “creating science and technology and promoting the harmonious development of nature, mankind and society”, TusTech University conducts extensive research from basic science to applied science. Tus National University is a private university in some of the most important fields today and is a meritocracy that recognizes and educates the best scientific talent. It is the only private university in Japan to produce Nobel Prize winners and the only private university in Asia to produce Nobel Prize winners. field of natural sciences.
Website: https://www.tus.ac.jp/en/mediarelations/
About Professor Kawahara of Tokyo University of Science
Takayuki Kawahara is a professor in the Department of Electrical Engineering, Tokyo University of Science, Japan. He received his Ph.D. Obtained a PhD from Kyushu University in 1993. Professor Kawahara’s current research is dedicated to sustainable electronics and has been cited more than 8500 times, with a special focus on low-power artificial intelligence (AI) devices and circuits, sensors, spin current applications and quantum computing technology. He has received several awards, including the 2014 IEICE Electronics Society Award and the Science and Technology Award (Development Category) in the Fiscal Year 2017 Science and Technology Commendation from the Minister of Education, Culture, Sports, Science and Technology of Japan.
Funding information
This research was partially supported by JSPS KAKENHI Grant No. 22H01559, Tokyo University of Science Entrepreneurship Grant (PoC Support Grant), and the Tokyo Metropolitan Government.
Research methods
Experimental Study
Research Topics
not applicable
Article title
Scalable fully coupled annealing system for 4096 rotations using 22nm CMOS LSI
Article publication date
January 30, 2024
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